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ADE7854/ADE7858/ADE7868/ADE7878
Table 39. MASK0 Register (Address 0xE50A)
Data Sheet
Bit
Location
0
Bit Mnemonic
AEHF
Default Value
0
Description
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total active
energy registers (AWATTHR, BWATTHR, or CWATTHR) changes.
1
FAEHF
0
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the fundamental
active energy registers (AFWATTHR, BFWATTHR, or CFWATTHR) changes. Setting this bit to1
does not have any consequence for ADE7854 , ADE7858 , and ADE7868 .
2
REHF
0
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total reactive
energy registers (AVARHR, BVARHR, CVARHR) changes. Setting this bit to1 does not have any
consequence for ADE7854 .
3
FREHF
0
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the fundamental
reactive energy registers (AFVARHR, BFVARHR, or CFVARHR) changes. Setting this bit to1
does not have any consequence for ADE7854 , ADE7858 , and ADE7868 .
4
VAEHF
0
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the apparent
energy registers (AVAHR, BVAHR, or CVAHR) changes.
5
LENERGY
0
When this bit is set to 1, in line energy accumulation mode, it enables an interrupt at the end
of an integration over an integer number of half line cycles set in the LINECYC register.
6
7
8
9
10
REVAPA
REVAPB
REVAPC
REVPSUM1
REVRPA
0
0
0
0
0
When this bit is set to 1, it enables an interrupt when the Phase A active power identified by
Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the Phase B active power identified by
Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the Phase C active power identified by
Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF1
datapath changes sign.
When this bit is set to 1, it enables an interrupt when the Phase A reactive power identified
by Bit 7 (REVRPSEL) in the ACCMODE register (total or fundamental) changes sign. Setting
this bit to1 does not have any consequence for ADE7854 .
11
REVRPB
0
When this bit is set to 1, it enables an interrupt when the Phase B reactive power identified
by Bit 7 (REVRPSEL) in the ACCMODE register (total or fundamental) changes sign. Setting
this bit to1 does not have any consequence for ADE7854 .
12
REVRPC
0
When this bit is set to 1, it enables an interrupt when the Phase C reactive power identified
by Bit 7 (REVRPSEL) in the ACCMODE register (total or fundamental) changes sign. Setting
this bit to1 does not have any consequence for ADE7854 .
13
14
REVPSUM2
CF1
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF2
datapath changes sign.
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at the
CF1 pin, that is, an active low pulse is generated. The interrupt can be enabled even if the
CF1 output is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of
power used at the CF1 pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register
(see Table 45).
15
16
CF2
CF3
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at CF2
pin, that is, an active low pulse is generated. The interrupt may be enabled even if the CF2
output is disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of power
used at the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE register (see Table 45).
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF3
pin, that is, an active low pulse is generated. The interrupt may be enabled even if the CF3
output is disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power
used at the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see Table 45).
17
DREADY
0
When this bit is set to 1, it enables an interrupt when all periodical (at 8 kHz rate) DSP
computations finish.
18
REVPSUM3
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF3
datapath changes sign.
31:19
Reserved
00 0000 0000
Reserved. These bits do not manage any functionality.
0000
Rev. H| Page 88 of 100
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